The present invention relates to copper (Cu) and/or Cu alloy metallization in semiconductor devices with improved planarity. The present invention is applicable to manufacturing high speed integrated circuits having submicron design features and high conductivity interconnect structures with high production through-put.
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require responsive changes in interconnection technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance and capacitance) interconnect pattern, particularly wherein submicron vias, contacts and trenches have high aspect ratios imposed by miniaturization.
Conventional semiconductor devices comprise a semiconductor substrate, typically doped monocrystalline silicon, and a plurality of sequentially formed dielectric interlayers and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor xe2x80x9cchipsxe2x80x9d comprising five or more levels of metallization are becoming more prevalent as device geometries shrink to submicron levels.
A conductive plug filling a via hole is typically formed by depositing an interlayer dielectric on a conductive layer comprising at least one conductive pattern, forming an opening through the interlayer dielectric by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the dielectric interlayer is typically removed by chemical mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the dielectric interlayer and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via hole section in communication with an upper trench section. The entire opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
Cu and Cu alloys have received considerable attention as a candidate for replacing Al in interconnect metallizations. Cu is relatively inexpensive, easy to process, and has a lower resistivity than Al. In addition, Cu has improved electrical properties, vis-à-vis W, making Cu a desirable metal for use as a conductive plug as well as conductive wiring.
An approach to forming Cu plugs and wiring comprises the use of damascene structures employing CMP, as in Teong, U.S. Pat. No. 5,693,563. However, due to Cu diffusion through interdielectric layer materials, such as silicon dioxide, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier metals include tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium-tungsten (TiW), tungsten (W), tungsten nitride (WN), titanium-titanium micride (Ti-TiN), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN) and silicon nitride for encapsulating Cu.
The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the dielectric interlayer, but includes interfaces with other metals as well.
In conventional CMP techniques, a wafer carrier assembly is rotated in contact with a polishing pad in a CMP apparatus. The polishing pad is mounted on a rotating turntable or platen driven by an external driving force. The wafers are typically mounted on a rotating turntable or platen driven by an external driving force. The wafers are typically mounted on a carrier or polishing head which provides a controllable force, i.e., pressure, urging the wafers against the rotating polishing pad. Thus, the CMP apparatus effects polishing or rubbing movement between the surface of each thin semiconductor wafer and the polishing pad while dispersing a polishing slurry containing abrasive particles in a reactive solution to effect both chemical activity and mechanical activity while applying a force between the wafer and a polishing pad.
Conventional polishing pads employed in abrasive slurry processing typically comprise a grooved porous polymeric surface, such as polyurethane, and the abrasive slurry varied in accordance with the particular material undergoing CMP. Basically, the abrasive slurry is impregnated into the pores of the polymeric surface while the grooves convey the abrasive slurry to the wafer processing is disclosed by Krywanczyk et al. in U.S. Pat. No. 5,842,910. Typical CMP is performed not only on a silicon wafer itself, but on various dielectric layers, such as silicon oxide, conductive layers, such as aluminum and copper, or a layer containing both conductive and dielectric materials as in damascene processing.
A distinctly different type of abrasive article from the above-mentioned abrasive slurry-type polishing pad is a fixed abrasive article, e.g., fixed abrasive polishing pad. Such a fixed abrasive article typically comprises a backing sheet with a plurality of geometric abrasive composite elements adhered thereto. The abrasive elements typically comprise a plurality of abrasive particles in a binder, e.g., a polymeric binder. During CMP employing a fixed abrasive article, the substrate or wafer undergoing CMP wears away the fixed abrasive elements thereby exposing the abrasive particles. Accordingly, during CMP employing a fixed abrasive article, a chemical agent is dispersed to provide the chemical activity, while the mechanical activity is provided by the fixed abrasive elements and abrasive particles exposed by abrasion with the substrate undergoing CMP. Thus, such fixed abrasive articles do not require the use of a slurry containing loose abrasive particles and advantageously reduce effluent treatment and dishing as compared to polishing pads that require an abrasive slurry. During CMP employing a fixed abrasive polishing pad, a chemical agent is applied to the pad, the agent depending upon the particular material or materials undergoing CMP. However, the chemical agent does not contain abrasive particles as in abrasive slurry-type CMP operations. Fixed abrasive articles are disclosed by Rutherford et al. in U.S. Pat. No. 5,692,950, Calhoun in U.S. Pat. No. 5,820,450, Haas et al. In U.S. Pat. No. 5,453,312 and Hibbard et al. in U.S. Pat. No. 5,454,844.
Fixed abrasive elements of conventional slurry-less type polishing pads are typically formed in various xe2x80x9cpositivexe2x80x9d geometric configurations, such as a cylindrical, cubical, truncated cylindrical, and truncated pyramidal shapes, as disclosed by Calhoun in U.S. Pat. No. 5,820,450. Conventional fixed abrasive articles also comprise xe2x80x9cnegativexe2x80x9d abrasive elements, such as disclosed by Ravipati et al. in U.S. Pat. No. 5,014,468.
In applying conventional planarization techniques, such as CMP, to Cu, it is extremely difficult to achieve a high degree surface uniformity, particularly across a surface extending from a dense array of Cu features, e.g., Cu lines, bordered by an open field. A dense array of metal (Cu) features is typically formed in an interlayer dielectric, such as a silicon oxide layer, by a damascene technique wherein trenches are initially formed. A barrier layer, such as a Ta-containing layer e.g., Ta, TaN, is then deposited lining the trenches and on the upper surface of the silicon oxide interlayer dielectric. Cu or a Cu alloy is then deposited, as by electroplating, electroless plating, physical vapor deposition (PVD) at a temperature of about 50xc2x0 C. to about 150xc2x0 C. or chemical vapor deposition (CVD) at a temperature under about 200xc2x0 C., typically at a thickness of about 8,000 xc3x85 to about 18,000 xc3x85. In planarizing the wafer surface after copper metallization, erosion and dishing are typically encountered, thereby decreasing the degree of surface uniformity or planarity and challenging the depth of focus limitations of conventional photolithographic techniques, particular with respect to achieving submicron dimensions, such as below about 0.25 micron. As used throughout this disclosure, the term, xe2x80x9cerosionxe2x80x9d denotes the height differential between the oxide in the open field and the height of the oxide within the dense array. As also used throughout this disclosure, the term xe2x80x9cdishingxe2x80x9d denotes a difference in height between the oxide and Cu within the dense array.
Erosion typically occurs within the dense array and is believed to be attributed in part to an increase in pressure due to the presence of recesses and, hence, less Cu, generating a pressure differential between the dense array and the open field. Consequently, the removal rate within the dense array is greater than the removal rate in the open field. Accordingly, the barrier layer is reached within the dense array before it is reached in the open field. In fact, conventionally, the oxide layer is reached within the dense array before Cu is completely removed in the open field. Upon removing the barrier layer in the open field, the oxide layer in the dense array is over-polished resulting in erosion. Due to the high selectivity of copper: oxide and copper: tantalum, the copper lines in the dense array are overpolished, thereby resulting in dishing.
There exists a need for high production through-put Cu CMP without erosion and dishing, or with significantly reduced erosion and dishing, thereby achieving a high degree of surface planarity suitable for photolithographic techniques in forming features having dimensions within the deep submicron range.
An advantage of the present invention is a method of planarizing Cu and Cu alloys by CMP at high production through-put with no or significantly reduced erosion and no or significantly reduced dishing and defects.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in party by a method of planarizing a wafer surface containing: an interlayer dielectric having an upper surface and a plurality of spaced apart openings; a barrier layer lining the openings and on the upper surface of the interlayer dielectric; and copper (Cu) or a Cu alloy filling the openings and on the interlayer dielectric; the method comprising the sequential steps of: chemical mechanical polishing (CMP) the wafer to remove the Cu or Cu alloy layer stopping on the barrier layer; and buffing the wafer to remove the barrier layer at zero or reversed selectivity with respect to Cu: barrier layer and Cu: interlayer dielectric to form a dense array of Cu or Cu alloy features.
Embodiments of the present invention include forming a Cu or Cu alloy interconnection structure comprising openings in a silicon oxide interlayer dielectric lined with a barrier layer, such as a Ta-containing barrier layer, e.g., Ta or TaN, and filled with Cu or a Cu alloy. Dishing is eliminated or at least significantly reduced by buffing with zero or reversed selectivity with respect to Cu: Ta or TaN and Cu: silicon oxide.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein embodiments of the present invention are described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.